The present invention relates generally to semiconductor memory devices and more particularly to multi-bit flash electrically erasable programmable read only memory (EEPROM) cells that utilize the phenomenon of hot electron injection to trap charge within a trapping dielectric material within the gate.
Memory devices for non-volatile storage of information are currently in widespread use today, being used in a myriad of applications. A few examples of non-volatile semiconductor memory include read only memory (ROM), programmable read only memory (PROM), erasable programmable read only memory (EPROM), electrically erasable programmable read only memory (EEPROM) and flash EEPROM.
Semiconductor ROM devices, however, suffer from the disadvantage of not being electrically programmable memory devices. The programming of a ROM occurs during one of the steps of manufacture using special masks containing the data to be stored. Thus, the entire contents of a ROM must be determined before manufacture. In addition, because ROM devices are programmed during manufacture, the time delay before the finished product is available could be six weeks or more. The advantage, however, of using ROM for data storage is the low cost per device. However, the penalty is the inability to change the data once the masks are committed to. If mistakes in the data programming are found they are typically very costly to correct. Any inventory that exists having incorrect data programming is instantly obsolete and probably cannot be used. In addition, extensive time delays are incurred because new masks must first be generated from scratch and the entire manufacturing process repeated. Also, the cost savings in the use of ROM memories only exist if large quantities of the ROM are produced.
Moving to EPROM semiconductor devices eliminates the necessity of mask programming the data but the complexity of the process increases drastically. In addition, the die size is larger due to the addition of programming circuitry and there are more processing and testing steps involved in the manufacture of these types of memory devices. An advantage of EPROMs are that they are electrically programmed, but for erasing, EPROMs require exposure to ultraviolet (UV) light. These devices are constructed with windows transparent to UV light to allow the die to be exposed for erasing, which must be performed before the device can be programmed. A major drawback to these devices is that they lack the ability to be electrically erased. In many circuit designs it is desirable to have a non-volatile memory device that can be erased and reprogrammed in-circuit, without the need to remove the device for erasing and reprogramming.
Semiconductor EEPROM devices also involve more complex processing and testing procedures than ROM, but have the advantage of electrical programming and erasing. Using EEPROM devices in circuitry permits in-circuit erasing and reprogramming of the device, a feat not possible with conventional EPROM memory. Flash EEPROMs are similar to EEPROMs in that memory cells can be programmed (i.e., written) and erased electrically but with the additional ability of erasing all memory cells at once, hence the term flash EEPROM. The disadvantage of flash EEPROM is that it is very difficult and expensive to manufacture and produce.
The widespread use of EEPROM semiconductor memory has prompted much research focusing on constructing better memory cells. Active areas of research have focused on developing a memory cell that has improved performance characteristics such as shorter programming times, utilizing lower voltages for programming and reading, longer data retention times, shorter erase times and smaller physical dimensions. One such area of research involves a memory cell that has an insulated gate. The following prior art reference is related to this area.
U.S. Pat. No. 4,173,766, issued to Hayes, teaches a metal nitride oxide semiconductor (MNOS) constructed with an insulated gate having a bottom silicon dioxide layer and a top nitride layer. A conductive gate electrode, such as polycrystalline silicon or metal, is placed on top of the nitride layer. A major disadvantage of this device is the difficulty in using it to construct a flash EEPROM. A consequence of using an oxide-nitride structure as opposed to an oxide-nitride-oxide structure is that during programming the charge gets distributed across the entire nitride layer. The absence of the top oxide layer lowers the ability to control where the charge is stored in the nitride layer.
Further, in the memory cell disclosed in Hayes, the nitride layer is typically 350 Angstroms thick. A thick nitride layer is required in Hayes"" device in order to achieve sufficient charge retention. Since the nitride can only tolerate relatively small internal electric fields, a thick layer of nitride is required to compensate. Due to the thick nitride layer, very high vertical voltages are needed for erasing. The relatively thick nitride layer causes the distribution of charge, i.e., the charge trapping region, to be very wide and a wider charge trapping region makes erasing the cell via the drain extremely difficult if not impossible. In addition, drain erasing is made difficult because of the increased thickness of the charge trapping layer. Thus, the memory cell taught by Hayes must have a thick nitride layer for charge retention purposes but at the expense of making it extremely difficult to erase the device via the drain, thus making the device impractical for flash EEPROM applications.
To erase the memory cell of Hayes, the electrons previously trapped in the nitride must be neutralized either by moving electrons out of the nitride or by transferring holes into the nitride. Hayes teaches an erase mode for his memory cell whereby the information stored on the nitride is erased by grounding the gate and applying a sufficient potential to the drain to cause avalanche breakdown. Avalanche breakdown involves hot hole injection into the nitride in contrast to electron injection. Avalanche breakdown, however, requires relatively high voltages and high currents for the phenomenon to occur. To lower the avalanche breakdown voltage, a heavily doped impurity is implanted into the channel between the source and the drain.
The hot holes are generated and caused to surmount the hole potential barrier of the bottom oxide and recombine with the electrons in the nitride. This mechanism, however, is very complex and it is difficult to construct memory devices that work in this manner. Another disadvantage of using hot hole injection for erase is that since the PN junction between the drain and the channel is in breakdown, very large currents are generated that are difficult to control. Further, the number of program/erase cycles that the memory cell can sustain is limited because the breakdown damages the junction area. The damage is caused by the very high local temperatures generated in the vicinity of the junction when it is in breakdown.
In addition, it is impractical to use the memory device of Hayes in a flash memory array architecture. The huge currents generated during erase using avalanche breakdown would cause significant voltage (i.e., IR), drops along the bit line associated with the memory cell in breakdown.
Another well known technique of erasing is to inject holes from the gate into the nitride layer. This mechanism, however, is very complex and difficult to control due to the higher mobility of holes versus electrons in the nitride. With elevated temperatures, the higher mobility of holes causes a large loss of charge retention and consequently lower threshold voltage deltas from the original programming threshold. Deep depletion phenomenon creates the need for a companion serial device to control the programming/erase process.
U.S. Pat. No. 5,168,334, issued to Mitchell et al., teaches a single transistor EEPROM memory cell. Mitchell, however, teaches an oxide-nitride-oxide (ONO) EEPROM memory cell wherein oxide-nitride-oxide layers are formed above the channel area and between the bit lines for providing isolation between overlying polysilicon word lines. The nitride layer provides the charge retention mechanism for programming the memory cell.
Although the memory device of Mitchell includes a top oxide layer, it is not very well suited for flash EEPROM applications. This is due to the very wide charge trapping region that must be programmed in order to achieve a sufficient delta in the threshold voltage between programming and reading. The Mitchell device is programmed and read in the forward direction. Since reading in the forward direction is less effective than reading in the reverse direction, the charge trapping region must be wider by default in order to distinguish between the programmed and unprogrammed states. A wider charge trapping region, however, makes the memory device very difficult to erase, thus making this device inefficient for flash EEPROM applications.
A single transistor ONO EEPROM device is disclosed in the technical article entitled xe2x80x9cA True Single-Transistor Oxide-Nitride-Oxide EEPROM Device,xe2x80x9d T. Y. Chan, K. K. Young and Chenming Hu, IEEE Electron Device Letters, March 1987. The memory cell is programmed by hot electron injection and the injected charges are stored in the oxide-nitride-oxide (ONO) layer of the device. This article teaches programming and reading in the forward direction. Thus, as in Mitchell, a wider charge trapping region is required to achieve a sufficiently large difference in threshold voltages between programming and reading. This, however, makes it much more difficult to erase the device.
Multi-bit transistors are known in the art. Most multi-bit transistors utilize multi-level thresholds to store more than one bit with each threshold level representing a different state. A memory cell having four threshold levels can store two bits. This technique has been implemented in a ROM by using implanting techniques and has also been attempted in FLASH and EEPROM memory. The multi-level threshold technique has not been applied to EPROM memory due to the fact that if the window of a threshold defining a given state is exceeded, a UV erase cycle must be performed which is very cumbersome and costly. In addition, to perform the UV erase, the chip must first be removed from the system which can be very problematic.
Achieving multiple thresholds in FLASH and EEPROM requires an initial erase cycle to bring all the memory cells below a certain threshold. Then, utilizing a methodical programming scheme, the threshold of each cell is increased until the desired threshold is reached. A disadvantage with this technique is that the programming process requires constant feedback which causes multi-level programming to be slow.
In addition, using this technique causes the window of operation to decrease meaning the margins for each state are reduced. This translates to a lower probability of making good dies and a reduction in the level of quality achieved. If it is not desired to sacrifice any margins while increasing the reliability of the cell, then the window of operation must be increased by a factor of two. This means operating at much higher voltages which is not desirable because it lowers the reliability and increases the disturbances between the cells. Due to the complexity of the multi-threshold technique, it is used mainly in applications where missing bits can be tolerated such as in audio applications.
Another problem with this technique is that the threshold windows for each state may change over time reducing the reliability. It must be guaranteed that using the same word line or bit line to program other cells will not interfere with or disturb the data in cells already programmed. In addition, the programming time itself increases to accommodate the multitude of different programming thresholds. Thus, the shifting of threshold windows for each state over time reduces the window of operation and consequently increases the sensitivity to disturbs.
The reduced margins for the threshold windows for the multiple states results in reduced yield. Further, in order to maintain quality and threshold margins, higher voltages are required. This implies higher electric fields in the channel which contributes to lower reliability of the memory cell.
In order to construct a multi-bit ROM memory cell, the cell must have four distinct levels that can be programmed. In the case of two levels, i.e., conventional single bit ROM cell, the threshold voltage programmed into a cell for a xe2x80x980xe2x80x99 bit only has to be greater than the maximum gate voltage, thus making sure the cell does not conduct when it is turned on during reading. It is sufficient that the cell conducts at least a certain amount of current to distinguish between the programmed and unprogrammed states. The current through a transistor can be described by the following equation.   I  =            1      Leff        ⁢          xe2x80x83        ⁢    K    ⁢          xe2x80x83        ⁢          (                        V          G                -                  V          T                    )      
Leff is the effective channel length, K is a constant, VG is the gate voltage and VT is the threshold voltage. However, in the multi-bit case, different thresholds must be clearly distinguishable which translates into sensing different read currents and slower read speed. Further, for two bits, four current levels must be sensed, each threshold having a statistical distribution because the thresholds cannot be set perfectly. In addition, there will be a statistical distribution for the effective channel length which will further widen the distribution of the read currents for each threshold level.
The gate voltage also affects the distribution of read currents. For the same set of threshold levels, varying the gate voltage directly results in a variation of the ratio between the read currents. Therefore the gate voltage must be kept very stable. In addition, since there are multiple levels of current, sensing becomes more complex than in the two level, i.e., single bit, cell.
The following prior art references are related to multi-bit semiconductor memory cells.
U.S. Pat. No. 5,021,999, issued to Kohda et al., teaches a non-volatile memory cell using an MOS transistor having a floating gate with two electrically separated segmented floating gates. The memory cell can store three levels of data: no electrons on either segment, electrons injected into either one of the two segments and electrons injected into both segments.
U.S. Pat. No. 5,214,303, issued to Aoki, teaches a two bit transistor which comprises a semiconductor substrate, a gate electrode formed on the substrate, a pair of source/drain regions provided in the substrate and an offset step portion formed in at least one of the source/drain regions and downwardly extending into the substrate in the vicinity of the gate electrode.
U.S. Pat. No. 5,394,355, issued to Uramoto et al., teaches a ROM memory having a plurality of reference potential transmission lines. Each reference potential transmission line represents a different level or state. Each memory cell includes a memory cell transistor able to connect one of the reference potential transmission lines to the corresponding bit line.
U.S. Pat. No. 5,414,693, issued to Ma et al., teaches a two bit split gate flash EEPROM memory cell structure that uses one select gate transistor and two floating gate transistors. In this invention essentially each bit is stored in a separate transistor.
U.S. Pat. No. 5,434,825, issued to Harari, teaches a multi-bit EPROM and EEPROM memory cell which is partitioned into three or more ranges of programming charge. The cell""s memory window is widened to store more than two binary states. Each cell is programmed to have one of the programmed states. To achieve more than two binary states, multiple negative and positive threshold voltages are used. The cell basically comprises a data storage transistor coupled to a series pass transistor. The data transistor is programmed to one of the predefined threshold states. Sensing circuitry distinguishes the different current levels associated with each programmed state.
The present invention discloses an apparatus for and method of programming, reading and erasing a two bit flash electrically erasable programmable read only memory (EEPROM). The two bit flash EEPROM memory cell is constructed having a charge trapping non-conducting dielectric layer sandwiched between two silicon dioxide layers. The nonconducting dielectric layer functions as an electrical charge trapping medium. The charge trapping layer is sandwiched between two layers of silicon dioxide which act as electrical insulators. A conducting gate layer is placed over the upper silicon dioxide layer. The two individual bits, i.e., left and right bits, are stored in physically different areas of the charge trapping region.
A novel aspect of the memory device is that while both bits are programmed in the conventional manner, using hot electron programming, each bit is read in a direction opposite that in which it was programmed with a relatively low gate voltage. For example, the right bit is programmed conventionally by applying programming voltages to the gate and the drain while the source is grounded. Hot electrons are accelerated sufficiently to be injected into a region of the trapping dielectric layer near the drain. The device, however, is read in the opposite direction from which it was written, meaning voltages are applied to the gate and the source while the drain is grounded. The left bit is similarly programmed and read by swapping the functionality of source and drain terminals. Programming one of the bits leaves the other bit with its information intact and undisturbed. Programming one of the bits does, however, have a very small effect on the other bit, e.g., slightly slower programming speed for the second bit.
Reading in the reverse direction is most effective when relatively low gate voltages are used. A benefit of utilizing relatively low gate voltages in combination with reading in the reverse direction is that the potential drop across the portion of the channel beneath the trapped charge region is significantly reduced. A relatively small programming region or charge trapping region is possible due to the lower channel potential drop under the charge trapping region. This permits much faster programming times because the effect of the charge trapped in the localized trapping region is amplified. Programming times are reduced while the delta in threshold voltage between the programmed versus unprogrammed states remains the same as when the device is read in the forward direction.
Another major benefit is that the erase mechanism of the memory cell is greatly enhanced. Both bits of the memory cell can be erased by applying suitable erase voltages to the gate and the drain for the right bit and to the gate and the source for the left bit so as to cause electrons to be removed from the charge trapping region of the nitride layer. Electrons move from the nitride through the bottom oxide layer to the drain or the source for the right and the left bits, respectively. Another benefit includes reduced wearout from cycling thus increasing device longevity. An effect of reading in the reverse direction is that a much higher threshold voltage for the same amount of programming is possible. Thus, to achieve a sufficient delta in the threshold voltage between the programmed and unprogrammed states of the memory cell, a much smaller region of trapped charge is required when the cell is read in the reverse direction than when the cell is read in the forward direction.
The erase mechanism is enhanced when the charge trapping region is made as narrow as possible. Programming in the forward direction and reading in the reverse direction permits limiting the width of the charge trapping region to a narrow region near the drain (right bit) or the source. This allows for much more efficient erasing of the memory cell.
Further, utilizing a thinner silicon nitride charge trapping layer than that disclosed in the prior art helps to confine the charge trapping region to a laterally narrower region near the drain. Further, the thinner top and bottom oxide sandwiching the nitride layer helps in retention of the trapped charge.
In addition, unlike prior art floating gate flash EEPROM memory cells, the bottom and top oxide thickness can be scaled due to the deep trapping levels that function to increase the potential barrier for direct tunneling. Since the electron trapping levels are so deep, thinner bottom and top oxides can be used without compromising charge retention.
Another benefit of localized charge trapping is that during erase, the region of the nitride away from the drain does not experience deep depletion since the erase occurs near the drain only. The final threshold of the cell after erasing is self limited by the device structure itself. This is in direct contrast to conventional single transistor floating gate flash memory cells which are plagued with deep depletion problems. To overcome these problems, manufacturers include complex circuitry to control the erase process in order to prevent or recover from deep depletion.
Another approach previously employed in the prior art to solve the deep depletion problem was to design the floating gate flash memory cell using a split gate design forming multiple transistors per cell. The split gate or double transistor constructions were necessary because the information carrying transistor, i.e., the floating gate transistor, potentially could be over erased. An over erase condition caused the threshold voltage of the cell to go too low. The second transistor, acting as a control transistor, prevented the floating gate transistor from being over erased.
Considerations of the two bit memory cell of the present invention are described hereinbelow. The first is the fact that reading in the reverse direction permits read through of the trapping region associated with the other bit. The second is that programming the device to a low VT, by clamping the word line voltage VWL, further enhances the margin for each bit. The margin is defined as the parameters that will program one of the bits without affecting the other.
Further, the locality of the trapped charge due to hot electron injection in combination with reverse reading permits two distinct charge trapping regions to be formed in a relatively short device whose Leff is approximately 0.2 microns. Also, utilizing a combination of positive VD and either zero or negative VG permits each bit to be erased separately.
The memory device also exhibits little or no disturb during programming. This is because during programming the drain voltage is only applied to the junction adjacent to the region where charge trapping is to occur.
It is important to note that a memory cell constructed in accordance with the present invention cannot store two bits utilizing programming in the forward direction and reading in the forward direction. This is due to the forward read requiring a wider charge trapping region to be programmed in order to achieve a sufficient delta in read currents for a one and a zero. Once one of the bits is programmed, the wider charge trapping region prevents read through to the other bit.